The Indian Institute of Science (IISc) has developed a design framework for next-generation analog computing chipsets that could be quicker and use less power than the digital chips found in most electronic gadgets.
The team developed a prototype of an analog chipset dubbed ARYABHAT-1 using their new design methodology (Analog Reconfigurable Technology And Bias-scalable Hardware for AI Tasks). This type of chipset is very useful for AI-based applications such as object or speech recognition (think Alexa or Siri) or those that demand enormous parallel computing operations at fast speeds.
Since the design process is straightforward and scalable, digital chips are used in the majority of electronic devices, particularly those involving computing. “However, analog has a significant advantage. Power and size will improve by orders of magnitude “Chetan Singh Thakur, assistant professor at IISc’s Department of Electronic Systems Engineering (DESE), whose lab is leading the effort to develop the analog chipset, explains. Analog computing has the potential to outperform digital computing in applications that do not require accurate computations because the former is more energy-efficient.
However, there are several technical hurdles to overcome while designing analog chips. Unlike digital chips, testing and co-design analog processors are difficult. Large-scale digital processors can be easily synthesized by compiling a high-level code, and the same design can be ported across different generations of technology development—say, from a 7 nm chipset to a 3 nm chipset—with minimal modifications.
Analog chips don’t scale easily—they need to be individually customized when transitioning to the next generation technology or to a new application—their design is expensive. Another challenge is that trading off precision and speed with power and area is not easy when it comes to analog design. In digital design, simply adding more components like logic units to the same chip can increase precision, and the power at which they operate can be adjusted without affecting the device performance.
To overcome these challenges, the team has designed a novel framework that allows the development of analog processors which scale just like digital processors. Their chipset can be reconfigured and programmed so that the same analog modules can be ported across different generations of process design and across different applications. “You can synthesize the same kind of chip at either 180 nm or at 7 nm, just like digital design,” adds Thakur.
Different machine learning architectures can be programmed on ARYABHAT, which, like digital CPUs, can operate reliably throughout a wide temperature range, according to the researchers. They also state that the architecture is “bias-scalable,” meaning that its performance remains constant when operational circumstances like as voltage or current are changed. This means that the same chipset can be tuned for low-energy Internet of Things (IoT) applications as well as high-speed operations like object identification.
The design framework was developed as part of IISc student Pratik Kumar’s Ph.D. work, and in collaboration with Shantanu Chakrabartty, Professor at the McKelvey School of Engineering, Washington University in St Louis (WashU), U.S., who also serves as WashU’s McDonnell Academy ambassador to IISc. “It’s good to see the theory of analog bias-scalable computing being manifested in reality and for practical applications,” says Chakrabartty, who had earlier proposed bias-scalable analog circuits.
The researchers have outlined their findings in two pre-print studies that are currently under peer review. They have also filed patents and are planning to work with industry partners to commercialize the technology.
The design framework was developed as part of IISc student Pratik Kumar’s Ph.D. work, and in collaboration with Shantanu Chakrabartty, Professor at the McKelvey School of Engineering, Washington University in St Louis (WashU), U.S., who also serves as WashU’s McDonnell Academy ambassador to IISc. “It’s good to see the theory of analog bias-scalable computing being manifested in reality and for practical applications,” says Chakrabartty, who had earlier proposed bias-scalable analog circuits.
The researchers have outlined their findings in two pre-print studies that are currently under peer review. They have also filed patents and are planning to work with industry partners to commercialize the technology
